I. Field of the Invention
This invention relates generally to a data processing system and related method, and more specifically to a system and related method for linking together a plurality of individual intracommunication bus systems to enable intercommunication therebetween.
II. Background Information
A simple data processing system generally includes a memory component, an input/output component, a processor component, and an intracommunication bus system along which the memory, input/output and processor components are distributed. This intracommunication bus system includes an address bus, a data bus and a control bus. The memory component stores information in addressable storage locations. The input/output component is employed to transfer information into and out of the data processing system over the intracommunication bus system. The processor component includes means for generating address signals over the address bus and control signals over the control bus of the intracommunication bus system and through utilization of these address and control signals causes information to be transmitted over the data bus of the intracommunication bus system between the processor component, memory component, and input/output component.
For example, with reference to the simple timing drawing of FIG. 1, at the start of a data transfer sequence an address signal is generated by the processor component over the address bus. This address signal identifies a particular location within the simple data processing system, for example, a particular memory location in the memory component or a particular input-output port. Simultaneous with or shortly after generation of the address signal, the processor component generates a read/write signal on the control bus which indicates whether a data word is to be read from or written into the location identified by the address signal on the address bus. If the control bus contains a read signal, data is to be read from the address signal location and inserted onto the data bus. If the control bus contains a write signal, data appearing on the data bus is to be written into the location identified by the address signal on the address bus.
After generation of the read/write signal on the control bus, and in response to that signal and in response to the address signal on the address bus, the corresponding data word read or write operation is undertaken. After completion of the read or write operation, a transfer complete signal is generated on the control bus indicating termination of the data transfer and the end of the data transfer sequence. In the case of a read operation, the transfer complete signal appears on the control bus after a data word has been read from the address corresponding to the address signal on the address bus and that data word has been inserted on the data bus. In the case of a write operation, the transfer complete signal is inserted on the control bus after the data word on the data bus has been written into the address location identified by the address signal on the address bus.
It should be understood that the data communication transfers referred to above with regard to FIG. 1 are greatly simplified and are presented by means of illustration and not limitation. Thus, in reality, a data processing system of the prior art may contain substantially more sophisticated control signals on the control bus than those indicated above in FIG. 1.
Data processing systems which utilize low cost microprocessors as the processor component are currently in demand because of the speed at which such systems are able to operate. Microprocessor-type data processing systems are known which have the capacity to communicate with one another, thereby forming a complex data processing system referred to as a multiprocessor system. In such a multiprocessor system, data stored in a memory component of one individual data processing system may be transferred to a second individual data processing system in order, for example, to allow parallel processing of the data. A transfer of data between two or more individual data processing systems requires an interconnecting architecture. In addition to the interconnecting architecture, a system arbitration is required for controlling the interconnection and to establish a priority between each individual data processor system.
In a typical multiprocessor system the interconnecting architecture includes a direct memory access (DMA) controller for each combination of individual data processing systems to be connected together. Each DMA controller includes an address generator and each DMA controller is assigned a unique address. When a first data processing system wishes to communicate with a second data processing system, a first processor component of the first data processing system employs data transfer related software in the first system to issue an address signal over the address bus of that system's intracommunication bus system, which address signal corresponds to the DMA controller that interconnects the first and second systems. After so addressing the appropriate DMA controller, the first processor component, again using the data transfer related software, sends data to that DMA controller over the data bus of that system, which data informs the DMA controller of the present address of the data to be transferred, the new address to which this data is to be transferred, and the number of words of data involved in the transfer. The DMA controller then uses this information and the DMA controller address generator to generate address signals for each system required to access and transfer between the two systems the block of data involved. After the transfer, the processor component of the recipient system accesses the data from the memory component of that system where the DMA controller stored that data.
Although this type of multiprocessor system is capable of interconnecting a plurality of separate data processing systems to establish communication between those data processing systems and, thereby, to provide extended memory capability, the operation of such multiprocessor system has proven to be slower than desired when small amounts of data are to be transferred. The processor component of any individual data processing system of the type described must use data transfer related software to access the DMA controller and thereby effect a data transfer. This software is often complex with numerous instruction sequences.
Accordingly, there exists a need for a multiprocessor system with increased data processing capabilities and extended memory capabilities, but which does not sacrifice the speed of system operation when small amounts of data are to be transferred. More specifically, there is a need for a multiprocessor system with an intercommunication scheme which does not require data transfer related software, but which can nevertheless easily access any memory location within the multiprocessor system, thereby meeting the speed requirements of multiprocessor systems while allowing for extended memory.